Key Skills

Job Description

We Are Actively Expanding The Crypto & Security Competence Centre (CCC&S) At NXP And We Have New Opportunities In Our Team For Digital Verification Engineers Working On Next-generation Security Technologies Such As Post-Quantum Cryptography (PQC) IP Secure SoC subsystems, including next-generation roots of trust High-assurance cryptographic accelerators for future platforms At CCC&S, we are also driving a significant transformation in how hardware is designed and verified by integrating AI directly into IC design and verification flows. The role is blended with traditional verification methods whilst the AI agents are being developed. Driven Verification – What You’ll Be Part Of In this role, you will contribute to a step-change in verification capability through: AI-driven verification automation – reducing regression effort while maintaining full coverage Intelligent debug and analysis – accelerating bug discovery and root-cause identification Automated test and vPlan generation – improving consistency and reducing human error We Are Also Actively Developing Advanced Capabilities Including AI-assisted RTL understanding and test explanation Conversational debug interfaces for waveform and design interaction AI-driven coverage closure and test prioritization This is not a future vision—this transformation is already underway within CCC&S workflows. What You’ll Be Doing As a key member of our growing team, you will: Lead the verification of advanced PQC and security IP, tackling complex, security-focused design challenges Define and drive verification strategy, leveraging AI and automation to enhance productivity and quality Architect and scale SystemVerilog/UVM verification environments for IP and subsystem-level validation Champion Constrained Random and Metrics-Driven Verification (MDV) methodologies Own and drive coverage closure, using data-driven insights for high-confidence sign-off Develop SystemVerilog Assertions (SVA) for protocol checking and early defect detection Collaborate closely with design and architecture teams to influence verification from early stages Mentor and support engineers, contributing to a high-performing and forward-looking team culture Why This Role Stands Out Work on cutting-edge cryptography technologies critical to future cybersecurity Help define how AI transforms verification workflows and methodologies Join a growing organisation where your input shapes tools, processes, and technical direction Take ownership of high-visibility, complex projects from concept to silicon Your Profile BSc., or MSc., degree in Electronics or Electrical Engineering. Strong hands-on experience with SystemVerilog for testbench development and verification. Proven expertise in UVM (Universal Verification Methodology), including component creation, sequences, drivers, monitors, and scoreboards. Solid understanding and practical use of Constrained Random Verification techniques. Experience with Metrics‑Driven Verification, including functional coverage and verification planning. Ability to write SystemVerilog Assertions (SVA) for protocol and design checking. Demonstrated success in achieving Coverage Closure across functional and code coverage metrics. Experience analysing coverage results and refining test strategies to close gaps. Strong debugging skills across simulations and complex verification environments. Knowledge of Formal Verification methods would be advantageous. If you're excited by the opportunity to work at the intersection of hardware, security, and AI, and want to contribute to technologies that will define the next decade, we invite you to apply! Remote / Hybrid working is applicable to this position. More information about NXP in the United Kingdom...

Core Responsibilities

Lead verification of post-quantum cryptography and security IP, defining verification strategies and building scalable SystemVerilog/UVM environments for IP and subsystem validation. Drive coverage closure and sign-off, develop assertions, apply AI and automation to verification workflows, and collaborate with design and architecture teams while mentoring engineers.

Requirements

Requires a BSc or MSc in Electronics or Electrical Engineering and strong hands-on SystemVerilog and UVM experience, including testbench components and sequences. Candidates should have practical constrained-random and metrics-driven verification experience, SVA skills, a record of closing coverage gaps, and strong debugging ability; formal verification knowledge is advantageous.