Job description

Fortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company. We are looking for a Hardware Security Engineer to design and secure our next-generation cryptographic engines. You will be responsible for the end-to-end RTL implementation of hardware crypto modules and integrating robust countermeasures directly into the logic to protect against physical attacks. We are looking for candidates with not only an exceptional skillset, but also an exceptional mindset, willing to go above and beyond to make our breakthrough product even better.

Job requirements

• Proven experience writing RTL (SystemVerilog/VHDL) for ASIC or FPGA.

• Deep understanding of cryptographic algorithms (AES, ECC, SHA) and how they translate to hardware logic.

• Hands-on experience implementing side-channel countermeasures (masking, thresholds).

• Familiarity with SCA tools (ChipWhisperer, etc.) is a strong plus.

Job responsibilities

• Crypto Module Design: Write high-quality, synthesized RTL (Verilog/VHDL) for hardware cryptographic accelerators, ensuring high performance and low latency.

• Countermeasure Implementation: Apply architectural and logic-level defenses directly into the crypto designs, including Masking (Boolean/Arithmetic), Hiding (shuffling, dummy cycles), and fault detection logic.

• Side-Channel Analysis: Evaluate your designs using SCA tools to simulate power and electromagnetic attacks (DPA/CPA) and verify that the implemented countermeasures effectively stop leakage.

• Security Verification: Work with verification teams to create test benches that specifically target edge cases in the cryptographic logic.

Additional information

The successful candidate will have the unique opportunity to participate in shaping the design of our groundbreaking product, contributing to the development of ultra-secure and high-performance SoC designs. They will be part of a dynamic and innovative team, working in a collaborative and challenging environment at the forefront of semiconductor technology.